- Proje Görevlileri:
- Türü-Bütçesi: AB FP7 Marie Curie grant no: 267266 - 222 Bin TL
- Başlangıç Yılı: 2010
- Süre (Yıl): 4
A current steering Digital to Analog Converter (DAC) is the enabling integrated circuit for high-speed waveform generation, with key applications such as UMTS cellular base stations, DOCSIS compliant digital TV broadcast, and RF test equipment. There is continuous demand for higher speed and higher resolution DACs that can generate waveforms at higher output frequencies with good linearity. The most important linearity metric of a high speed DAC is Spurious Free Dynamic Range (SFDR), and other measures such as Intermodulation Distortion (IMD) or Adjacent Channel Leakage Ratio (ACLR) depend on SFDR. Even with the state of the art DACs, SFDR drops very fast with increasing output frequency. Best 16- bit, high-speed DACs can achieve 95 dB SFDR at Fout = 1MHz, however, SFDR drops to less than 70 dB at Fout > 100 MHz. To generate more accurate waveforms at high frequencies, it is crucial to identify, understand and address the dynamic error mechanisms of DACs. In a nutshell, the project proposal consists of identification, avoidance and elimination of dynamic error mechanisms, demonstrated by a 16-bit, 2 Giga-sample-per-second (GSPS) DAC, on a 0.18u CMOS process.